Sr Asic Design Verification Engineer

Cisco UK

Base: $165,000.00 - $241,400.00; bonus/equity: eli...
Onsite
System verilog experience required
Uvm methodology expertise needed
7+ years asic verification experience
Join the Cisco Silicon One team to develop unified silicon architecture for web scale networks

Job Summary

  • Join the Cisco Silicon One team to develop unified silicon architecture for web scale networks.
  • Architect and maintain block, cluster, and top-level Design Verification environment infrastructure using System Verilog and UVM.
  • Enjoy a unique blend of large organization resources with startup culture growth opportunities including onsite gym and healthcare.

Matching Summary

Join the Cisco Silicon One team to develop unified silicon architecture for web scale networks.

Salary

Base: $165,000.00 - $241,400.00; Bonus/Equity: Eligible for annual bonuses and restricted stock units; Benefits: Medical, dental, vision, 401(k) match, paid time off

Skills & Requirements

Must-have

  • System Verilog experience required
  • UVM methodology expertise needed
  • 7+ years ASIC verification experience
  • Block or full chip level verification
  • Testbench component construction skills

Nice-to-have

  • Post-silicon lab bring-up experience
  • Emulation platform usage (Veloce/Palladium)
  • Linux C/C++ Python scripting skills
  • Networking domain knowledge preferred
  • Startup culture collaboration style

Key Requirements

  • Bachelor's degree + 7 years experience OR Master's + 4 years OR PhD + 1 year
  • Prior experience in System Verilog and UVM
  • Experience verifying blocks/clusters or full chip level for ASIC

Work Rights

Not specified

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