The role involves leading the development of pre-silicon infrastructure and post-silicon validation efforts for Cadence's High Speed SERDES Test chips
Job Summary
The role involves leading the development of pre-silicon infrastructure and post-silicon validation efforts for Cadence's High Speed SERDES Test chips.
Cadence offers a collaborative 'One Cadence – One Team' culture that encourages creativity and provides multiple avenues for employee learning and development.
Candidates must possess deep expertise in physical layer electrical validation on protocols like PCIe, USB, DP, Ethernet, SRIO, JESD204, or DDRIO.
Matching Summary
The role involves leading the development of pre-silicon infrastructure and post-silicon validation efforts for Cadence's High Speed SERDES Test chips.
Skills & Requirements
Must-have
Post-Silicon Physical Layer Electrical Validation
High Speed SERDES protocol experience
Lab equipment usage (Oscilloscopes, BERT)
Test chip hardware and software architecture
6-10 years experience with Btech or 4-8 with Mtech
Nice-to-have
Experience managing small teams of 2+ members
FPGA design and PCB layout prototyping skills
Passion for analog and digital circuit design
Mentoring new hires and conducting interviews
Verilog RTL coding familiarity
Key Requirements
6-10 years experience (Btech) or 4-8 years (Mtech)
Deep experience with at least one High speed SERDES protocol
Hands-on experience with lab equipment like Oscilloscopes and BERT