Senior Pre-silicon Verification Engineer

Intel

Hillsboro, Oregon, US
Base: $141,910.00-232,190.00 usd; bonus/equity: st...
Hybrid
Uvm
Systemverilog
Mixed-signal verification
Intel's Central Engineering Group is committed to transforming engineering processes while expanding market reach through internal product development and external ASIC design services

Job Summary

  • Intel's Central Engineering Group is committed to transforming engineering processes while expanding market reach through internal product development and external ASIC design services.
  • Perform comprehensive functional verification of clock generator IPs including PLL/FLL to ensure designs meet specification requirements.
  • We offer a total compensation package that ranks among the best in the industry, consisting of competitive pay, stock bonuses, and benefit programs.

Matching Summary

Intel's Central Engineering Group is committed to transforming engineering processes while expanding market reach through internal product development and external ASIC design services.

Salary

Base: $141,910.00-232,190.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • UVM
  • SystemVerilog
  • mixed-signal verification
  • clock generator IP verification
  • AMS simulations

Nice-to-have

  • data-driven approach
  • scalable impact
  • cutting-edge technologies
  • world-class engineers

Key Requirements

  • Bachelor's degree in Electronics / Electrical/ Computer Engineering
  • 3+ years of experience in Design Verification and Validation
  • 3+ years of experience in scripting languages
  • Post graduate degree in Electronics/Electrical/Computer Engineering
  • Experience with debug methodologies
  • Experience with RTL development

Work Rights

Not specified

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