Physical Design Engineer - Soc

Samsung Electronics

Bangalore, Karnataka, India
Complex soc top physical implementation
Synthesis place and route sta timing closure
Power user of icc dc pt vslp redhawk calibre
The role involves complex SOC top physical implementation for next-generation mobile application processors and modem subsystems

Job Summary

  • The role involves complex SOC top physical implementation for next-generation mobile application processors and modem subsystems.
  • Candidates must demonstrate strong understanding of timing, power, and area trade-offs while optimizing PPA metrics.
  • Samsung Semiconductor India Research offers a foundation to work on cutting-edge technologies including AI/ML and 5G/6G solutions.

Matching Summary

The role involves complex SOC top physical implementation for next-generation mobile application processors and modem subsystems.

Skills & Requirements

Must-have

  • Complex SOC top physical implementation
  • Synthesis Place and Route STA timing closure
  • Power user of ICC DC PT VSLP Redhawk Calibre
  • Experience with large SOC designs over 20M gates
  • Deep sub-micron design familiarity 8nm 5nm

Nice-to-have

  • Top level floor planning experience
  • Hierarchical and top-down design methodology
  • Recent successful SOC tape-outs
  • Strong scripting skills in Perl or Tcl

Key Requirements

  • 5+ years of relevant experience
  • B.Tech B.E M.Tech M.E degree
  • Expertise in block level and full-chip SDC cleanup

Work Rights

Not specified

Tailored Resume

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