Principal Design Verification Engineer

GlobalFoundries

$153,000.00 - $265,000.00 py
Not specified
Systemverilog
Uvm-based environments
Constrained random verification
GlobalFoundries is seeking a Principal Design Verification Engineer with over 8 years of experience to join its CPU verification team, focusing on the verification of processor components. Candidates should possess strong skills in SystemVerilog, UVM, and scripting, with a solid understanding of CPU architectures

Job Summary

  • Perform functional verification of CPU cores and related subsystems, focusing on coherency and cache controllers.
  • Develop and execute verification plans, including testbench creation and test case development using SystemVerilog, C, and Assembly.
  • Automate regression and verification flows using scripting languages and collaborate with senior engineers and architects to ensure design quality and performance.

Matching Summary

Match Score: 85

GlobalFoundries is seeking a Principal Design Verification Engineer with over 8 years of experience to join its CPU verification team, focusing on the verification of processor components. Candidates should possess strong skills in SystemVerilog, UVM, and scripting, with a solid understanding of CPU architectures.

Salary

$153,000.00 - $265,000.00

Skills & Requirements

Must-have

  • SystemVerilog
  • UVM-based environments
  • constrained random verification
  • CPU architectures
  • cache and coherency concepts
  • scripting languages

Nice-to-have

  • RISC-V architecture exposure
  • interconnect protocols knowledge
  • FPGA prototyping experience
  • emulation platforms experience

Key Requirements

  • 8+ years of experience
  • Bachelor’s degree in Electronics/Electrical/Computer Engineering
  • Design verification experience
  • CPU or SoC verification experience
  • SystemVerilog, UVM, constrained random verification
  • Familiarity with CPU architectures
  • Basic understanding of cache and coherency
  • Strong scripting skills

Work Rights

Not specified

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