Senior Asic Physical Design Technical Lead

Cisco UK

Base: $210,600.00 to $305,100.00; bonus/equity: el...
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Fullchip floorplan and rtl-to-gdsii flow
Hierarchical implementation and partitioning
Static timing analysis and power integrity
** Cisco UK is seeking a Senior ASIC Physical Design Technical Lead to join the Common Hardware Group, focusing on the design and development of advanced ASICs for networking hardware. The role requires extensive experience in physical design, particularly with fullchip activities and modern process technologies. **

Job Summary

  • This role involves shaping Cisco's groundbreaking silicon solutions by designing advanced ASICs for the industry's unified silicon architecture spanning top-of-rack switches to web-scale data centers.
  • The successful candidate will lead full-chip activities from floorplanning through static timing analysis and physical verification with a focus on performance, power, and die size optimization.
  • Employees are eligible for comprehensive benefits including medical, dental, vision insurance, 401(k) matching, paid parental leave, and grants of Cisco restricted stock units.

Matching Summary

Match Score: 75

** Cisco UK is seeking a Senior ASIC Physical Design Technical Lead to join the Common Hardware Group, focusing on the design and development of advanced ASICs for networking hardware. The role requires extensive experience in physical design, particularly with fullchip activities and modern process technologies. **

Salary

Base: $210,600.00 to $305,100.00; Bonus/Equity: Eligible for annual bonuses and restricted stock units; Benefits: Medical, dental, vision, 401(k), paid time off

Skills & Requirements

Must-have

  • Fullchip floorplan and RTL-to-GDSII flow
  • Hierarchical implementation and partitioning
  • Static timing analysis and power integrity
  • UPF low-power design methodologies
  • EDA tools Innovus Tempus Primetime Calibre
  • Signoff methodology with foundry vendors

Nice-to-have

  • AI tool usage for productivity improvements
  • Python scripting for flow automation
  • Custom clock tree synthesis experience
  • Leadership and mentorship capabilities
  • Post-silicon validation feedback integration

Key Requirements

  • Bachelor's degree plus 12+ years Physical Design experience
  • Master's degree plus 8+ years Physical Design experience
  • PhD plus 5+ years Physical Design experience
  • Experience with 7nm/5nm/3nm process technologies
  • Proven track record of RTL2GDSII tapeouts

Work Rights

Not specified

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