Base: $154,000 to $286,000 (california); bonus/equ...
M.s. or ph.d. in electrical engineering
3+ years high speed serdes and phy experience
Hands-on lab experience with oscilloscopes and vnas
This is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems as a key contributor to advanced high speed IP products
Job Summary
This is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems as a key contributor to advanced high speed IP products.
The role involves working on test chip package design optimization, evaluation board design, and providing channel models for chip designers.
Candidates will benefit from competitive compensation including bonus, equity, and comprehensive benefits such as medical, dental, vision, and a 401(k) plan.
Matching Summary
This is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems as a key contributor to advanced high speed IP products.
Salary
Base: $154,000 to $286,000 (California); Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, 401(k) match, stock purchase plan, medical/dental/vision
Skills & Requirements
Must-have
M.S. or Ph.D. in Electrical Engineering
3+ years high speed SerDes and PHY experience
Hands-on lab experience with oscilloscopes and VNAs
Proficiency with Sigrity Clarity/PowerSI or Ansys HFSS/SIwave