Principal Design Engineer – Ai Soc / Subsystem Lead

Intel Corporation

Folsom, California, United States
Base: $220,920.00-311,890.00 usd; bonus/equity: st...
Hybrid
10+ years engineering experience
7+ years rtl design implementation
Bachelor's or master's degree in ee/ce/cs
Intel Corporation is seeking a Principal Design Engineer for their AI SoC organization, focusing on the development of advanced AI hardware. The ideal candidate should possess extensive experience in RTL design for ASIC/SoC development, along with strong technical and communication skills

Job Summary

  • This role involves defining, implementing, and validating complex SoC IP blocks to power next-generation AI solutions ranging from edge devices to data center accelerators.
  • The successful candidate will drive post-silicon validation, debug, and performance analysis while ensuring designs meet stringent power, performance, and security targets.
  • Intel offers a competitive total compensation package including stock bonuses, health benefits, retirement plans, and a hybrid work model for this position.

Matching Summary

Match Score: 85

Intel Corporation is seeking a Principal Design Engineer for their AI SoC organization, focusing on the development of advanced AI hardware. The ideal candidate should possess extensive experience in RTL design for ASIC/SoC development, along with strong technical and communication skills.

Salary

Base: $220,920.00-311,890.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, vacation programs

Skills & Requirements

Must-have

  • 10+ years engineering experience
  • 7+ years RTL design implementation
  • Bachelor's or Master's degree in EE/CE/CS
  • Verilog/SystemVerilog expertise
  • SoC IP block architecture
  • Power performance security requirements

Nice-to-have

  • Cross-functional collaboration skills
  • Mentorship of junior engineers
  • Python/TCL scripting proficiency
  • Secure development practices knowledge
  • Strong communication abilities

Key Requirements

  • 10+ years total engineering experience
  • 7+ years ASIC/SoC RTL design experience
  • Bachelor's or Master's degree required
  • Position of Trust background check required

Work Rights

Not specified

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