Design Engineer I

Cadence

PUNE, India
C++
Systemc/transaction level modeling (tlm)
Soc architecture understanding
Lead the activity of virtual platform definition, which will be used for early SW development for the customer

Job Summary

  • Lead the activity of virtual platform definition, which will be used for early SW development for the customer.
  • Develop the model and integrate with other models or infrastructure components, testing, and debug.
  • Work closely with architecture, RTL design, design verification, emulation, and software teams to build, debug, and deploy your models.

Matching Summary

Lead the activity of virtual platform definition, which will be used for early SW development for the customer.

Skills & Requirements

Must-have

  • C++
  • SystemC/Transaction Level Modeling (TLM)
  • SoC architecture understanding
  • functional models for SW development
  • embedded SW on bare metal and Linux

Nice-to-have

  • interpersonal and communication skills
  • ability to work in teams
  • collaborate with colleagues

Key Requirements

  • Experience in developing and using functional models
  • Good understanding of embedded SW
  • Strong programming concepts
  • In depth understanding of SoC architecture
  • Excellent interpersonal and communication skills

Work Rights

Not specified

Tailored Resume

Cover Letter