Director Of Engineering – Asic Design

NXP USA INC.

15+ years asic front-end design experience
Proven delivery of complex socs in production silicon
Expertise in verilog/systemverilog rtl design
The role requires leading the front-end design of advanced SoCs optimized for AI inference, networking, and edge compute workloads

Job Summary

  • The role requires leading the front-end design of advanced SoCs optimized for AI inference, networking, and edge compute workloads.
  • Candidates must drive architectural trade-off analysis across compute, memory, interconnect, and I/O subsystems while ensuring QC-clean RTL delivery.
  • The position involves building and mentoring high-performing teams to foster a culture of engineering excellence and accountability.

Matching Summary

The role requires leading the front-end design of advanced SoCs optimized for AI inference, networking, and edge compute workloads.

Skills & Requirements

Must-have

  • 15+ years ASIC front-end design experience
  • Proven delivery of complex SoCs in production silicon
  • Expertise in Verilog/SystemVerilog RTL design
  • Strong background in microarchitecture and SoC integration
  • Experience with low-power design techniques

Nice-to-have

  • Foster a culture of engineering excellence
  • Ability to influence across organizations and geographies
  • Collaboration with system and software teams
  • Mentoring and team-building capability

Key Requirements

  • 15+ years of experience in ASIC front-end design
  • Proven delivery of complex SoCs / AI accelerators in production silicon
  • Strong background in architecture, RTL, verification, timing, power, and silicon bring-up

Work Rights

Not specified

Tailored Resume

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