Principal Analog Ic Designer

Cadence

San Jose, California, US
Base: $136,500 to $253,500; bonus/equity: eligible...
7+ years cmos serdes experience
High-speed i/o ic design expertise
Jitter and signal equalization knowledge
The Principal Analog IC Designer is responsible for designing analog/mixed signal IC circuit blocks from concept through final verification

Job Summary

  • The Principal Analog IC Designer is responsible for designing analog/mixed signal IC circuit blocks from concept through final verification.
  • Candidates must possess a minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design.
  • The role offers competitive compensation including bonus, equity, and comprehensive benefits like medical, dental, vision, and 401(k) matching.

Matching Summary

The Principal Analog IC Designer is responsible for designing analog/mixed signal IC circuit blocks from concept through final verification.

Salary

Base: $136,500 to $253,500; Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, holidays, 401(k), stock purchase plan

Skills & Requirements

Must-have

  • 7+ years CMOS SerDes experience
  • High-speed I/O IC design expertise
  • Jitter and signal equalization knowledge
  • Driver and Receiver circuit design
  • CAD tools for simulation and layout

Nice-to-have

  • Knowledge of common SerDes standards
  • Cadence tool proficiency
  • Lab test experience
  • Strong problem-solving skills
  • Cooperative team environment

Key Requirements

  • MS or PhD in EE
  • Minimum 7 years experience
  • Proficiency in <28nm technologies
  • Experience with >10Gbps designs

Work Rights

Not specified

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