This role involves designing and maintaining UVM-based verification environments for cutting-edge semiconductor technologies like 56G/112G SERDES and security IPs
Job Summary
This role involves designing and maintaining UVM-based verification environments for cutting-edge semiconductor technologies like 56G/112G SERDES and security IPs.
Engineers will develop comprehensive test plans covering protocol corner cases, timing jitter, and security threat scenarios to ensure high reliability.
The position offers the opportunity to work across diverse domains at one of Samsung's largest R&D centers outside Korea, focusing on innovation and creativity.
Matching Summary
This role involves designing and maintaining UVM-based verification environments for cutting-edge semiconductor technologies like 56G/112G SERDES and security IPs.
Skills & Requirements
Must-have
SystemVerilog and UVM expertise
High-speed serial protocol knowledge
Formal verification and SVA skills
VCS Xcelium Questa simulation tools
Security IP verification experience
Nice-to-have
Mentoring junior engineers
CI/CD pipeline integration
Low-power design considerations
Collaboration with architecture teams
Key Requirements
5-6 years of hands-on verification experience
B.E./B.Tech/M.Tech in Electrical or Computer Engineering