Senior Integrated Circuit Designer - Layout

ASTERA LABS SINGAPORE PRIVATE LIMITED

Singapore
Layout for highspeed analog ic designs
Finfet technology experience
Emir and antenna drc rules awareness
The role involves designing and developing layouts for sophisticated advanced node CMOS products including PLL, DLL, and ADCs

Job Summary

  • The role involves designing and developing layouts for sophisticated advanced node CMOS products including PLL, DLL, and ADCs.
  • Candidates must possess expertise in minimizing parasitics, managing EMIR, and adhering to antenna rules within finFET technology.
  • The position requires a bachelor's degree in electrical engineering with at least two years of experience in highspeed analog IC layout development.

Matching Summary

Match Score: 75

The role involves designing and developing layouts for sophisticated advanced node CMOS products including PLL, DLL, and ADCs.

Skills & Requirements

Must-have

  • Layout for highspeed analog IC designs
  • FinFET technology experience
  • EMIR and antenna DRC rules awareness
  • Floor planning and parasitic minimization
  • Integration of PLL, DLL, ADC circuits

Nice-to-have

  • SKILL and TCL scripting skills
  • Team-oriented work style
  • Cross-timezone collaboration ability

Key Requirements

  • Bachelor's degree in electrical engineering
  • 2+ years experience in highspeed analog IC layouts
  • Experience with layout extraction tools

Work Rights

Not specified

Tailored Resume

Cover Letter