This role involves leading a specialized team to define, design, and verify complex ASIC packaging for Cisco Silicon One, which drives over 90% of global IP traffic
Job Summary
This role involves leading a specialized team to define, design, and verify complex ASIC packaging for Cisco Silicon One, which drives over 90% of global IP traffic.
The successful candidate will develop design rules for ultra-high-speed signaling and collaborate with layout teams to optimize solutions across interposers, substrates, and PCBs.
Cisco offers a competitive salary range of $210,600 to $305,100, along with comprehensive benefits including equity grants, flexible vacation time, and paid parental leave.
Matching Summary
This role involves leading a specialized team to define, design, and verify complex ASIC packaging for Cisco Silicon One, which drives over 90% of global IP traffic.
Salary
Base: $210,600.00 - $305,100.00; Bonus/Equity: Eligible for annual bonuses and restricted stock units; Benefits: Medical, dental, vision, 401(k), paid time off, and volunteer days
Skills & Requirements
Must-have
10+ years signal and power integrity experience
High-speed ASIC tape-out experience
Keysight ADS and Ansys HFSS expertise
56G PAM4 and SerDes architecture knowledge
Bachelor's degree in Electrical Engineering
Nice-to-have
Experience leading small to medium technical teams
Advanced node packaging (5nm, 3nm) background
HBM or high-speed memory interface SI experience
MATLAB or Python scripting skills
UCIe or die-to-die interface knowledge
Key Requirements
Bachelor's degree + 10 years experience OR Master's + 8 years OR PhD + 5 years
Proven track record of multiple high-speed ASIC tape-outs from package perspective
Deep expertise in transmission line theory and electromagnetics
Hands-on experience with Cadence APD for layout review
Work Rights
Must live within commuting distance of San Jose, CA office