Asic Design Technical Lead

Cisco UK

San Jose, USA
Base: $183,800.00 - $303,100.00; bonus/equity: not...
On-site
Verilog rtl implementation
Micro-architecture development
Timing closure
Participate in chip architecture definition and discussions, author design specifications, and implement Verilog RTL to meet timing and performance requirements

Job Summary

  • Participate in chip architecture definition and discussions, author design specifications, and implement Verilog RTL to meet timing and performance requirements.
  • Mentor junior engineers, collaborate with verification and physical design teams, and triage, debug, and root cause simulation, software bring-up, and customer failures.
  • Perform diagnostic and post silicon validation tests in the lab and contribute to defining and evolving design methodology.

Matching Summary

Participate in chip architecture definition and discussions, author design specifications, and implement Verilog RTL to meet timing and performance requirements.

Salary

Base: $183,800.00 - $303,100.00; Bonus/Equity: Not specified; Benefits: Medical, dental, vision, 401(k) match, paid parental leave, disability, life insurance, stock units

Skills & Requirements

Must-have

  • Verilog RTL implementation
  • Micro-architecture development
  • Timing closure
  • Debugging simulation failures

Nice-to-have

  • Design methodology evolution
  • Collaboration with verification team
  • Collaboration with physical design team
  • Python, Perl, TCL scripting

Key Requirements

  • Bachelor's degree or Master's degree
  • 10+ years ASIC Design experience
  • 8+ years ASIC Design experience
  • Verilog/System Verilog programming
  • Interactive and waveform debug experience
  • Resolving setup and hold timing violations
  • Developing micro-architecture solutions

Work Rights

Not specified

Tailored Resume

Cover Letter