Asic Dft Engineering Technical Leader

Cisco

Bangalore, India
Hardware design-for-test features
Jtag protocols experience
Post-silicon validation experience
You will be involved in crafting groundbreaking next generation networking chips

Job Summary

  • You will be involved in crafting groundbreaking next generation networking chips.
  • The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
  • You will help lead to drive the DFT and quality process through the entire Implementation flow.

Matching Summary

You will be involved in crafting groundbreaking next generation networking chips.

Skills & Requirements

Must-have

  • Hardware Design-for-Test features
  • Jtag protocols experience
  • Post-silicon validation experience

Nice-to-have

  • Verilog design experience
  • Strong verbal communication skills
  • Scripting skills in Tcl, Python

Key Requirements

  • Bachelor's or Master’s Degree in Electrical or Computer Engineering
  • At least 10 years of experience
  • Experience with ATPG and EDA tools

Work Rights

Not specified

Tailored Resume

Cover Letter