Asic Design Verification Engineer

Cisco UK

System verilog experience
Uvm methodology expertise
Testbench construction skills
The role involves developing test benches and contributing to verification infrastructure for next-generation switching ASICs

Job Summary

  • The role involves developing test benches and contributing to verification infrastructure for next-generation switching ASICs.
  • Candidates will collaborate with Cisco's best-in-class switching solution team to integrate Nexus systems and ACI with software platforms.
  • Responsibilities include defining new DV methodologies, enhancing existing testbenches, and participating in emulation and ASIC bring-up efforts.

Matching Summary

The role involves developing test benches and contributing to verification infrastructure for next-generation switching ASICs.

Skills & Requirements

Must-have

  • System Verilog experience
  • UVM methodology expertise
  • Testbench construction skills
  • Constrained random DV environments
  • ASIC design and verification flow

Nice-to-have

  • C++ basic knowledge
  • Python Perl TCL shell scripting
  • High speed Ethernet protocol knowledge
  • Emulation testing experience
  • Collaborative team-focused mindset

Key Requirements

  • Bachelor's or master's degree in EE and CE
  • Hands-on experience in System Verilog and UVM
  • Ability to debug issues independently

Work Rights

Not specified

Tailored Resume

Cover Letter