Senior Principal Design Engineer

Cadence

Hyderabad, India
10-15 years dft experience
Scan insertion techniques
Atpg and mbist expertise
The role involves working on cutting-edge technology within an environment that encourages creativity and innovation to make a global impact

Job Summary

  • The role involves working on cutting-edge technology within an environment that encourages creativity and innovation to make a global impact.
  • Candidates will be responsible for executing chip tape-outs and post-silicon bring-up using industry-standard tools like Cadence Tessent.
  • The company promotes a collaborative 'One Cadence – One Team' culture focused on employee well-being and diverse career development opportunities.

Matching Summary

The role involves working on cutting-edge technology within an environment that encourages creativity and innovation to make a global impact.

Skills & Requirements

Must-have

  • 10-15 years DFT experience
  • Scan insertion techniques
  • ATPG and MBIST expertise
  • JTAG IEEE 1149.1/1149.6 standards
  • Gate level simulation SDF
  • Post-silicon ATE bring up
  • Cadence Tessent tools proficiency

Nice-to-have

  • Perl/Tcl scripting skills
  • Cross-domain collaboration
  • Strong communication abilities
  • High sense of ownership
  • Global team interaction

Key Requirements

  • BE/BTech/ME/MTech degree or equivalent
  • 5 to 15 years relevant experience
  • Experience with chip tape out and ATE bring up

Work Rights

Not specified

Tailored Resume

Cover Letter