Design Engineering Architect — Memory Modeling Portfolio

BETA CAE Systems International AG

Gyeonggi, South Korea
Hybrid
Ufs/unipro/mphy/rmmi protocol stack expertise
Systemverilog/verilog rtl design
Hardware emulation platforms
This role sits at the intersection of deep protocol expertise and direct partnership with our customers

Job Summary

  • This role sits at the intersection of deep protocol expertise and direct partnership with our customers.
  • Serve as the primary Korea-based customer interface for protocol integration, system-level debugging, and solutions consulting across the UFS/Unipro/MPHY/RMMI stack.
  • The MMP R&D team develops and sustains a world-class memory model IP library spanning UFS/Unipro/MPHY/RMMI, SDRAM families (DDRx, LPDDRx, HBMx), NAND Flash, DFI PHY, and hybrid memory technologies.

Matching Summary

This role sits at the intersection of deep protocol expertise and direct partnership with our customers.

Skills & Requirements

Must-have

  • UFS/Unipro/MPHY/RMMI protocol stack expertise
  • SystemVerilog/Verilog RTL design
  • Hardware emulation platforms
  • Customer interface and debugging
  • Advanced English fluency

Nice-to-have

  • Collaborative team spirit
  • Customer relationship building
  • Cross-cultural communication
  • Mentoring junior engineers
  • Protocol breadth beyond UFS

Key Requirements

  • Master’s degree or PhD with 8+ years experience
  • 10+ years relevant industry experience
  • Deep UFS/Unipro/MPHY/RMMI protocol expertise
  • SystemVerilog/Verilog RTL design and verification
  • Advanced English written and verbal fluency

Work Rights

Not specified

Tailored Resume

Cover Letter