Place And Route Design Automation Engineer

Altera

San Jose, California, United States
Base: $113,700 - $162,000 usd; bonus/equity: incen...
Place and route tool development
Fpga physical design experience
Tcl perl python scripting
Altera is seeking a motivated engineer to develop automated Place & Route tools and flows for next-generation FPGA silicon

Job Summary

  • Altera is seeking a motivated engineer to develop automated Place & Route tools and flows for next-generation FPGA silicon.
  • The role requires strong hands-on experience with industry-standard EDA vendor tools like Synopsys and Cadence in production environments.
  • Candidates must possess deep knowledge of physical design fundamentals including floorplanning, placement, routing, and static timing analysis.

Matching Summary

Altera is seeking a motivated engineer to develop automated Place & Route tools and flows for next-generation FPGA silicon.

Salary

Base: $113,700 - $162,000 USD; Bonus/Equity: Incentive opportunities available based on performance; Benefits: Not specified

Skills & Requirements

Must-have

  • Place and Route tool development
  • FPGA physical design experience
  • Tcl Perl Python scripting
  • Synopsys Cadence EDA tools
  • Static timing analysis expertise

Nice-to-have

  • Cross-functional collaboration skills
  • Debugging complex flow issues
  • Multi-geo team experience
  • Best practices promotion

Key Requirements

  • Bachelor's degree in Electrical or Computer Engineering
  • 3+ years industry experience in semiconductor design automation
  • 3+ years hands-on Place and Route experience
  • 3+ years coding experience in Tcl, Perl, and Python
  • Eligible for required U.S. export authorizations

Work Rights

Must be eligible for required U.S. export authorizations

Tailored Resume

Cover Letter