Job Summary

• Altera is looking for a talented and driven Principal Verification Engineer to design, develop, validate, and/or debug software abstractions and frameworks for acceleration with FPGAs.
• Key responsibilities include collaborating with architects, defining verification strategies, developing reusable verification environments using SystemVerilog and UVM, and executing simulation regressions.
• The role requires a Bachelor's or Master's degree in a related field with 10+ years of experience in ASIC or FPGA design verification.

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Skills & Requirements

Key Requirements

• 10+ years of experience
• Bachelor's or Master's degree
• Verilog or VHDL expertise
• System Verilog expertise
• UVM-based testbenches experience

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