Lead Design Engineer - Verification

Cadence

Shanghai, China
Systemverilog
Uvm
Amba, pcie, usb, mipi or ddr/lpddr
Looking for a skilled VLSI Design Verification Engineer with 3–5 years of hands-on experience to join our team supporting SOC design projects for leading customers

Job Summary

  • Looking for a skilled VLSI Design Verification Engineer with 3–5 years of hands-on experience to join our team supporting SOC design projects for leading customers.
  • Will play a key role in bridging communication between local teams and global stakeholders.
  • Contribute to the development and enhancement of verification environments and reusable testbenches.

Matching Summary

Looking for a skilled VLSI Design Verification Engineer with 3–5 years of hands-on experience to join our team supporting SOC design projects for leading customers.

Skills & Requirements

Must-have

  • SystemVerilog
  • UVM
  • AMBA, PCIe, USB, MIPI or DDR/LPDDR
  • RTL verification
  • verification plans

Nice-to-have

  • ARM/RISC-V Processor integration
  • collaboration with design teams
  • customer and internal engineering teams support

Key Requirements

  • 3-5 years of experience in VLSI/SOC design verification
  • Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field

Work Rights

Not specified

Tailored Resume

Cover Letter