Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans
Job Summary
Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.
Matching Summary
Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
Skills & Requirements
Must-have
SystemVerilog and UVM
coverage-driven verification
assertion-based verification
Python or Perl scripting
Nice-to-have
industry-standard protocols
collaborative team environment
Key Requirements
9+ years of experience in ASIC or FPGA design verification
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
Expertise in Verilog or VHDL and SystemVerilog
Strong hands-on experience in developing UVM-based testbenches