The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation
Job Summary
The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.
Must be able to work independently to develop test-plans, and related test-sequences in UVM to generate stimuli and work collaboratively with RTL designers to debug failures.
Must have prior experience using Verification IPs from 3rd party vendors for communication protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc.
Matching Summary
The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.
Skills & Requirements
Must-have
UVM
C/C++
System Verilog
RTL simulation
CoSimulation
Emulation
PCI-Express (Gen-3 and above)
Ethernet
Infiniband
DDR
NVMe
USB
VIP abstraction layers
Nice-to-have
Professional attitude
Entrepreneurial
Open-mind behavior
Can-do attitude
Think and act fast
Key Requirements
2+ years' experience
Bachelor’s in EE required
Experience with integrating C/C++ in System Verilog environments using DPI/PLI
Ability to use scripting tools (Perl/Python)
Experience in developing infrastructure and tests
Develop user-controlled random constraints
Experience writing assertions, cover properties and analyzing coverage data