Sta Synthesis Engineer

Samsung Semiconductor India Research

Bangalore, Karnataka, India
Sta fundamentals aocv pocv signal integrity
Primetime or tempus tool experience
Full chip timing constraint development
The role involves complete ownership of timing constraints at both full chip and subsystem levels for Samsung's cutting-edge semiconductor solutions

Job Summary

  • The role involves complete ownership of timing constraints at both full chip and subsystem levels for Samsung's cutting-edge semiconductor solutions.
  • Engineers will drive timing convergence and perform RTL PPA analysis to optimize power, performance, and area trade-offs.
  • This position requires strong analytical skills to work with diverse teams including RTL, DFT, and Physical Design on industry-leading technologies.

Matching Summary

The role involves complete ownership of timing constraints at both full chip and subsystem levels for Samsung's cutting-edge semiconductor solutions.

Skills & Requirements

Must-have

  • STA fundamentals AOCV POCV signal integrity
  • PrimeTime or Tempus tool experience
  • Full chip timing constraint development
  • UPF based static low power check
  • TCL Python Perl automation scripting

Nice-to-have

  • Pre and post layout timing debug skills
  • Cross-functional stakeholder management
  • Power optimization techniques knowledge
  • 5G 6G Neural processor domain exposure

Key Requirements

  • 4 to 7 years of relevant experience
  • B.Tech B.E M.Tech or M.E degree
  • Hands-on experience with EDA tools

Work Rights

Not specified

Tailored Resume

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