Lead Analog Serdes Architect/design Engineer

Intel

Santa Clara, California, US
Base: $220,920.00-311,890.00 usd; bonus/equity: st...
Hybrid
High-speed serial links design
Analog cmos/bicmos designs
Mixed-signal integrated circuits
Defining circuit architecture and enabling designs meeting power, and performance for next generation optical interconnects based on system specifications

Job Summary

  • Defining circuit architecture and enabling designs meeting power, and performance for next generation optical interconnects based on system specifications.
  • As part of the team developing key integrated circuit components the engineer must be able to work collaboratively leading block level development.
  • We offer a total compensation package that ranks among the best in the industry.

Matching Summary

Defining circuit architecture and enabling designs meeting power, and performance for next generation optical interconnects based on system specifications.

Salary

Base: $220,920.00-311,890.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • High-speed serial links design
  • Analog CMOS/BiCMOS designs
  • Mixed-Signal integrated circuits
  • PAM4/NRZ links design
  • Full-chip designs and verification

Nice-to-have

  • Optical communications familiarity
  • Package/test setup design experience
  • Collaborative team player

Key Requirements

  • MS in Electrical Engineering
  • 8+ years of experience
  • SerDes blocks design experience
  • Inductor, TIA, modulator driver design
  • Precision analog circuits design

Work Rights

Not specified

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