Sr Design Engineering Architect

Cadence

Bangalore, India
Rtl design and development
Verilog
System verilog
The role is for PCIe Architect with ARM CPU subsystem architecture, including memory subsystem design, IO and cache subsystems

Job Summary

  • The role is for PCIe Architect with ARM CPU subsystem architecture, including memory subsystem design, IO and cache subsystems.
  • The work involved will be addition of new features into the RTL, working with existing RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.
  • We’re doing work that matters. Help us solve what others can’t.

Matching Summary

The role is for PCIe Architect with ARM CPU subsystem architecture, including memory subsystem design, IO and cache subsystems.

Skills & Requirements

Must-have

  • RTL design and development
  • Verilog
  • System Verilog
  • UVM based environment usage
  • CPU subsystem architecture
  • memory subsystem design
  • IO and cache subsystems

Nice-to-have

  • addition of new features into RTL
  • working with existing RTL
  • ensuring customer configurations are clean
  • supporting customers
  • design is clean for LINT and CDC

Key Requirements

  • BE/BTech/ME/MTech - Electrical / Electronics / VLSI
  • 6-16 years core RTL Design experience
  • System Verilog experience
  • UVM based environment usage / debugging required
  • Architecture and design of CPU subsystem required
  • PCIe/CXL/IDE experience highly desirable

Work Rights

Not specified

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