Senior Ip Logic Design Engineer

Intel Retiree Medical Plan Trust

Santa Clara, California, US
Base: $190,610.00-269,100.00 usd; bonus/equity: st...
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Rtl coding in verilog or systemverilog
Memory coherency protocols
Interconnect technologies
** Intel is seeking a Senior IP Logic Design Engineer to work on memory systems and interconnect technologies for AI and data center SoCs. The role requires extensive experience in RTL coding and memory coherency protocols, with a focus on collaboration and innovation within a team-oriented environment. **

Job Summary

  • Develop the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
  • Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.
  • We offer a total compensation package that ranks among the best in the industry.

Matching Summary

Match Score: 75

** Intel is seeking a Senior IP Logic Design Engineer to work on memory systems and interconnect technologies for AI and data center SoCs. The role requires extensive experience in RTL coding and memory coherency protocols, with a focus on collaboration and innovation within a team-oriented environment. **

Salary

Base: $190,610.00-269,100.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • RTL coding in Verilog or SystemVerilog
  • Memory coherency protocols
  • Interconnect technologies
  • Performance modeling and analysis
  • Logic design for IP blocks

Nice-to-have

  • AI/ML accelerator design
  • Data center SoC design
  • Scripting languages for automation
  • Software-hardware co-design

Key Requirements

  • 10+ years in SoC design
  • MS/PhD in Electrical Engineering, Computer Engineering, or related field
  • Experience in memory systems
  • Experience with coherency protocols
  • RTL coding experience

Work Rights

Not specified

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