Soc Physical Design Timing Engineer

Intel

Bangalore, India
Hybrid
10+ years physical implementation experience
Primetime tool expertise
Tcl perl shell scripting skills
The candidate will be responsible for STA and timing closure activities of Intel SoCs and partitions

Job Summary

  • The candidate will be responsible for STA and timing closure activities of Intel SoCs and partitions.
  • This role requires hands-on experience with industry standard tools like Primetime and strong scripting skills in TCL, Perl, or Shell.
  • Candidates must possess a Bachelor's or Master's degree in Electrical/Electronics Engineering with over 10 years of relevant experience.

Matching Summary

The candidate will be responsible for STA and timing closure activities of Intel SoCs and partitions.

Skills & Requirements

Must-have

  • 10+ Years Physical Implementation experience
  • Primetime tool expertise
  • TCL Perl Shell scripting skills
  • SoC cycle understanding
  • Timing closure and ECO generation

Nice-to-have

  • Strong analytical problem solving skills
  • Self-motivated with initiative
  • Ability to work in diverse teams
  • Driving new methodologies
  • Multitasking capabilities

Key Requirements

  • Bachelor or Master of Engineering degree
  • 10+ years of Physical Implementation experience
  • Experience with Timing Closure methodologies

Work Rights

Not specified

Tailored Resume

Cover Letter