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UST Global is seeking an ATE Test Engineer for their Singapore office, responsible for executing test plans and supporting product life cycles. The ideal candidate should have extensive experience in ATE test program development, silicon debug, and proficiency in relevant programming languages.
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Job Summary
The role involves planning and executing pattern bring-up, validation plans, and yield attainment strategies based on strict schedules.
Candidates must possess practical knowledge of silicon debug, including implementing test specifications and developing patterns for Verigy 93K platforms.
The position requires working with cross-functional teams including design, package, and quality to support product life cycle activities.
Matching Summary
Match Score: 75
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UST Global is seeking an ATE Test Engineer for their Singapore office, responsible for executing test plans and supporting product life cycles. The ideal candidate should have extensive experience in ATE test program development, silicon debug, and proficiency in relevant programming languages.
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Skills & Requirements
Must-have
Verigy 93K ATE platform experience
Scan/ATPG methodologies knowledge
Silicon debug using ATE tools
Unix and Windows proficiency
Java Perl Python scripting skills
Nice-to-have
Experience with Lean XP Agile Scrum
Knowledge of JTAG IEEE 1149.1 specification
Background in analog mixed-signal DFT
Strong collaborative capabilities
Statistical analysis expertise
Key Requirements
Completed at least 2 full product cycles from Pre-silicon to Post silicon
Academic background in Computer Science or Digital Logic
Proficiency in diagnostic tools like logic analyzers and oscilloscopes