Hardware description languages vhdl verilog system verilog
Digital simulation debugging and failure analysis
The role focuses on verifying new and existing features for Intel's next-generation CPU IP to ensure a bug-free final design
Job Summary
The role focuses on verifying new and existing features for Intel's next-generation CPU IP to ensure a bug-free final design.
Engineers will develop validation test plans, simulation environments including bus functional models and checkers, and achieve functional coverage goals.
Candidates must work effectively in a cross-site team environment while collaborating with design engineers and micro-architects to deliver high-quality output against deadlines.
Matching Summary
The role focuses on verifying new and existing features for Intel's next-generation CPU IP to ensure a bug-free final design.
Skills & Requirements
Must-have
System Verilog UVM/OVM test bench development
Hardware description languages VHDL Verilog System Verilog
Digital simulation debugging and failure analysis
Functional coverage analysis and goal achievement
C/C++ Perl Ruby Python Unix scripting
Nice-to-have
Intel Architecture ISA and x86 assembly knowledge
Formal verification tools JasperGold IFV Questa VC Formal
Cross-site team collaboration experience
Strong problem-solving and initiative skills
Key Requirements
Bachelor's degree in EE/CE/CS with 3+ years experience OR Master's with 2+ years
Experience with hardware description languages and test bench development
Proficiency in programming languages such as C/C++, Perl, Ruby, Python, and Unix