$122,440.00-232,190.00 usd; not specified; health,...
Hybrid
System verilog & uvm testbench development
Constrained-random stimulus generation
Coverage metrics and closure
Perform comprehensive functional verification of IP or subsystem logic blocks to ensure compliance with specification requirements
Job Summary
Perform comprehensive functional verification of IP or subsystem logic blocks to ensure compliance with specification requirements.
Develop and execute detailed verification plans, test benches, and verification environments with comprehensive coverage metrics.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
Matching Summary
Perform comprehensive functional verification of IP or subsystem logic blocks to ensure compliance with specification requirements.
Salary
$122,440.00-232,190.00 USD; Not specified; health, retirement, and vacation
Skills & Requirements
Must-have
System Verilog & UVM testbench development
constrained-random stimulus generation
coverage metrics and closure
Python or other scripting language
Synopsys VCS, Cadence Xcelium, or Mentor Questa
version control systems (Git, Perforce)
Nice-to-have
AI/ML-driven verification
power-aware verification
CPU/GPU architecture verification
emulation platforms (Palladium, Veloce, Zebu)
Key Requirements
6+ years of experience in digital design verification
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
Master's degree in Electrical Engineering, Computer Engineering, or related field with 5+ years of experience