This role requires leading full chip or major block physical implementation from RTL to GDSII for cutting-edge semiconductor products
Job Summary
This role requires leading full chip or major block physical implementation from RTL to GDSII for cutting-edge semiconductor products.
The successful candidate will drive design methodologies to optimize power, performance, and area targets while ensuring aggressive schedule adherence.
Responsibilities include mentoring junior engineers and collaborating with RTL, DFT, and CAD teams to resolve integration issues.
Matching Summary
This role requires leading full chip or major block physical implementation from RTL to GDSII for cutting-edge semiconductor products.
Skills & Requirements
Must-have
10+ years physical design experience
Advanced technology nodes 7nm 5nm
Synopsys Fusion Compiler or Innovus
Full chip RTL to GDSII implementation
Static timing analysis and closure
Power integrity IR drop EM analysis
Tcl Perl Python scripting proficiency
Nice-to-have
Mentoring junior engineers
Global team collaboration skills
Innovative solution development
Strong problem-solving abilities
Key Requirements
Bachelor's or Master's degree in Electrical Engineering