Google is seeking a System on a Chip (SoC) Design for Test (DFT) Engineer to work on developing innovative silicon solutions for its consumer products. The role involves defining and implementing advanced DFT methodologies and strategies for digital or mixed-signal chips to enhance performance and efficiency
Job Summary
This role involves defining, implementing, and deploying advanced DFT methodologies for next-generation System on a Chips.
The team is responsible for developing custom silicon solutions that power Google's direct-to-consumer products and AI infrastructure.
Engineers will work on critical test strategies including memory BIST, scan chains, and logic built-in self-test to ensure high test quality.
Matching Summary
Match Score: 85
Google is seeking a System on a Chip (SoC) Design for Test (DFT) Engineer to work on developing innovative silicon solutions for its consumer products. The role involves defining and implementing advanced DFT methodologies and strategies for digital or mixed-signal chips to enhance performance and efficiency.
Salary
Not specified; Not specified; Not specified
Skills & Requirements
Must-have
System on a Chip DFT architecture
Memory Built-In Self Test MBIST
Automatic Test Pattern Generation ATPG
Hierarchical DFT implementation
Scan chains and DFT compression
Test Access Point TAP controller design
Nice-to-have
Mixed-signal chip experience
Post silicon debug collaboration
Innovation in AI hardware
High-performance computing background
Key Requirements
Experience with digital or mixed-signal chips
Expertise in DFT strategy and architecture definition