Synthesis & Front-end Implementation Engineer

NXP Semiconductors

**
Synopsys design compiler or fusion compiler
Static timing analysis (sta) with primetime
Formal verification using lec tools
** NXP Semiconductors is seeking a Synthesis & Front-End Implementation Engineer to optimize RTL designs into gate-level netlists, focusing on performance, power, and area targets for complex IP blocks. The ideal candidate should have at least 2 years of experience in digital ASIC/SoC design, particularly in synthesis and front-end implementation. **

Job Summary

  • This role is crucial for translating RTL designs into optimized gate-level netlists while meeting performance, power, and area targets.
  • The engineer will develop robust timing constraints and conduct static timing analysis to achieve target frequencies and ensure timing closure.
  • Candidates must possess strong scripting skills in Tcl, Python, or Perl to automate synthesis flows and design analysis.

Matching Summary

Match Score: 75

** NXP Semiconductors is seeking a Synthesis & Front-End Implementation Engineer to optimize RTL designs into gate-level netlists, focusing on performance, power, and area targets for complex IP blocks. The ideal candidate should have at least 2 years of experience in digital ASIC/SoC design, particularly in synthesis and front-end implementation. **

Skills & Requirements

Must-have

  • Synopsys Design Compiler or Fusion Compiler
  • Static Timing Analysis (STA) with PrimeTime
  • Formal verification using LEC tools
  • UPF low-power design techniques
  • Tcl Python Perl scripting automation

Nice-to-have

  • DFT principles knowledge
  • Collaborative team environment skills
  • Excellent problem-solving abilities

Key Requirements

  • Bachelor's or Master's degree in Electrical or Computer Engineering
  • 2+ years of experience in digital ASIC/SoC design
  • Proficiency with industry-standard synthesis and STA tools

Work Rights

Not specified

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