Full-chip Physical Design Engineer

Cisco UK

Bachelor's or master's degree in electrical engineering
Minimum of 3 years experience in asic design
Experience in deep submicron cmos technologies
The team is redefining silicon technology by managing full-chip physical implementation from RTL to GDSII

Job Summary

  • The team is redefining silicon technology by managing full-chip physical implementation from RTL to GDSII.
  • Engineers will perform critical tasks including gate-level netlist synthesis, floorplanning, and routing using advanced Clock Tree Architectures.
  • The role requires optimizing designs to achieve industry-leading power, performance, and area metrics while maintaining design integrity.

Matching Summary

The team is redefining silicon technology by managing full-chip physical implementation from RTL to GDSII.

Skills & Requirements

Must-have

  • Bachelor's or Master's degree in Electrical Engineering
  • Minimum of 3 years experience in ASIC design
  • Experience in deep submicron CMOS technologies
  • Comprehensive knowledge of full design cycle RTL to GDSII

Nice-to-have

  • Proficiency in Synopsys or Cadence PnR tools
  • Strong scripting skills for automation
  • Experience with analog IP physical integration
  • Collaboration with package and power integrity teams

Key Requirements

  • Bachelor's or Master's degree in Electrical Engineering or Computer Science
  • Minimum 3 years of experience in ASIC design and verification
  • Experience in deep submicron CMOS technologies

Work Rights

Not specified

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