Job Summary

• Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.
• Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
• Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).

Matching Summary

Skills & Requirements

Key Requirements

• 5+ years of experience
• Bachelor's or Master's degree
• Verilog or VHDL
• SystemVerilog
• UVM-based testbenches

Work Rights