Sta Cad/methodology Engineer

Cisco UK

Yerevan, Armenia
Hybrid
Static timing analysis (sta)
Sta signoff flows automation
Timing constraint development (sdc)
This role offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs by leading the development of scalable STA flows and automation

Job Summary

  • This role offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs by leading the development of scalable STA flows and automation.
  • You will contribute to the development, maintenance, and automation of STA signoff flows for complex SoC designs and assist with timing constraint development for multi-mode, multi-corner analysis.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond, working as a team to make really big things happen on a global scale.

Matching Summary

This role offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs by leading the development of scalable STA flows and automation.

Skills & Requirements

Must-have

  • Static Timing Analysis (STA)
  • STA signoff flows automation
  • timing constraint development (SDC)
  • TCL and Python scripting
  • timing closure support

Nice-to-have

  • collaborative attitude
  • continuous learning
  • Unix/Linux development environment

Key Requirements

  • 4+ years ASIC/SoC design experience
  • Bachelor's or Master's degree
  • STA fundamentals understanding
  • Experience with PrimeTime/Tempus
  • Proficiency in TCL/Python

Work Rights

Not specified

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