Indclutch is seeking a Design Verification Engineer to develop and validate software frameworks for FPGA acceleration, focusing on embedded, data center, and communication clients. The ideal candidate will have over three years of experience in ASIC or FPGA design verification, along with proficiency in SystemVerilog, UVM, and scripting languages
Job Summary
Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs.
Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM.
Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.
Matching Summary
Match Score: 85
Indclutch is seeking a Design Verification Engineer to develop and validate software frameworks for FPGA acceleration, focusing on embedded, data center, and communication clients. The ideal candidate will have over three years of experience in ASIC or FPGA design verification, along with proficiency in SystemVerilog, UVM, and scripting languages.
Skills & Requirements
Must-have
SystemVerilog and UVM
constrained-random verification environments
coverage-driven verification
assertion-based verification
Python or Perl scripting
Nice-to-have
industry-standard protocols
formal verification methods
collaborative, cross-functional team environment
Key Requirements
3+ years of experience in ASIC or FPGA design verification
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
Expertise in Verilog or VHDL and SystemVerilog
Strong hands-on experience in developing UVM-based testbenches
Familiarity with industry-standard protocols (AMBA, PCIe, Ethernet) is a plus