Base: not specified; bonus/equity: employee stock ...
Rtl design experience with synthesis
Static timing analysis and closure expertise
Formal verification and gate-level simulations
This role involves defining micro-architecture and driving RTL implementation for complex functional blocks in custom AI accelerators and CPUs using advanced process nodes
Job Summary
This role involves defining micro-architecture and driving RTL implementation for complex functional blocks in custom AI accelerators and CPUs using advanced process nodes.
The successful candidate will own end-to-end delivery of assigned blocks from architecture definition through tape-out, collaborating with cross-functional teams on verification and physical design.
Marvell offers comprehensive benefits including an employee stock purchase plan, family support programs, and robust mental health resources to support employees at every stage.
Matching Summary
This role involves defining micro-architecture and driving RTL implementation for complex functional blocks in custom AI accelerators and CPUs using advanced process nodes.
Salary
Base: Not specified; Bonus/Equity: Employee stock purchase plan available; Benefits: Comprehensive financial well-being and family support programs
Skills & Requirements
Must-have
RTL design experience with synthesis
Static timing analysis and closure expertise
Formal verification and gate-level simulations
Low-power design methodologies including UPF
SoC architectures and interface protocols like AXI PCIe
Nice-to-have
Micro-architecture design in AI/ML accelerators
Proficiency in Python Perl Tcl scripting
Experience with SerDes CXL die-to-die interfaces
Background in advanced packaging techniques
Key Requirements
Bachelor's degree with 10+ years experience OR Master's with 5+ years
Eligibility to access export-controlled information under US law
Work Rights
Must be eligible to access export-controlled information (US citizens, lawful permanent residents, or protected individuals)