The role involves designing and maintaining UVM-based verification environments for cutting-edge semiconductor technologies like 56G/112G SERDES and security IPs
Job Summary
The role involves designing and maintaining UVM-based verification environments for cutting-edge semiconductor technologies like 56G/112G SERDES and security IPs.
Engineers will develop comprehensive test plans covering protocol corner cases, timing jitter, and security threat scenarios to ensure high reliability.
Candidates are expected to mentor junior verification engineers and contribute to the IPD verification methodology library within a diverse global team.
Matching Summary
The role involves designing and maintaining UVM-based verification environments for cutting-edge semiconductor technologies like 56G/112G SERDES and security IPs.
Skills & Requirements
Must-have
SystemVerilog and UVM expertise
High-speed serial protocol knowledge
Formal verification and SVA skills
VCS Xcelium Questa simulation tools
Security IP verification experience
Nice-to-have
Mentoring junior engineers
CI/CD pipeline integration
Low-power design considerations
Cross-domain collaboration
Innovation and creativity focus
Key Requirements
5-6 years of hands-on verification experience
B.E./B.Tech/M.Tech in Electrical or Computer Engineering
Strong understanding of class-based verification and randomization