Ingénieur Vérification Asic R&d (f/h)

Atos SE

Les Clayes-sous-Bois, France
On-site
Uvm verification methodology
Constraint-random/coverage-driven
Systemverilog/c++ environment development
Participate in the verification of a complex ASIC using Constraint-Random, Coverage Driven methodologies based on the UVM standard

Job Summary

  • Participate in the verification of a complex ASIC using Constraint-Random, Coverage Driven methodologies based on the UVM standard.
  • Develop verification environments (UVM-SystemVerilog/C++), tests, and coverage models, while tracking, analyzing, and debugging simulation errors.
  • Atos offers a competitive compensation package, flexible remote work options, and professional development opportunities.

Matching Summary

Participate in the verification of a complex ASIC using Constraint-Random, Coverage Driven methodologies based on the UVM standard.

Skills & Requirements

Must-have

  • UVM verification methodology
  • Constraint-Random/Coverage-Driven
  • SystemVerilog/C++ environment development
  • Simulation tools and coverage tracking

Nice-to-have

  • Strong problem-solving skills
  • Adaptability and ability to multitask
  • Team player with collaborative spirit
  • Professional bilingualism (French/English)

Key Requirements

  • Proven experience in complex SoC/ASIC and IP verification
  • Experience with UVM methodology
  • Experience in Constraint-Random/Coverage-Driven environments
  • Object-oriented programming mastery

Work Rights

Not specified

Tailored Resume

Cover Letter