Asic Physical Design Technical Leader

Cisco UK

Yerevan, Armenia
Hybrid
Rtl-to-gdsii physical implementation
Complex socs or large subsystem designs
Clock tree synthesis (cts)
Join a world-class Physical Design team at the forefront of advanced SoC development, responsible for delivering groundbreaking silicon solutions

Job Summary

  • Join a world-class Physical Design team at the forefront of advanced SoC development, responsible for delivering groundbreaking silicon solutions.
  • Drive macro-level RTL-to-GDSII physical implementation and signoff for complex SoCs or large subsystem designs, ensuring high-quality results.
  • Mentor junior engineers, establish best practices, and partner with CAD, methodology, and EDA vendors to improve flows and enable new technologies.

Matching Summary

Join a world-class Physical Design team at the forefront of advanced SoC development, responsible for delivering groundbreaking silicon solutions.

Skills & Requirements

Must-have

  • RTL-to-GDSII physical implementation
  • complex SoCs or large subsystem designs
  • Clock Tree Synthesis (CTS)
  • routing, and signoff convergence
  • PPA (power, performance, area) optimization
  • STA, physical and formal verification
  • EM/IR analysis

Nice-to-have

  • technical leadership and mentoring
  • cross-functional alignment
  • methodology improvements
  • collaboration with CAD/flow teams
  • AI era solutions

Key Requirements

  • Bachelor's or Master's degree
  • 10+ years experience in ASIC physical design
  • Proven track record leading physical design through tapeout
  • Deep expertise in synthesis, place-and-route
  • Experience with industry-standard tools

Work Rights

Not specified

Tailored Resume

Cover Letter