NXP USA INC. is seeking an experienced Senior Static Timing Analysis (STA) Engineer to join their IC design team in Tianjin, China. This role involves leading timing signoff activities for complex SoC projects and requires strong collaboration with various design teams to ensure robust timing closure
Job Summary
Lead timing signoff activities for complex SoC projects, ensuring robust timing closure across multiple process, voltage, and temperature corners.
Own full-chip static timing analysis and signoff for advanced-node SoC designs, developing and maintaining STA constraints and timing methodologies.
Provide technical leadership in methodology development, tool evaluation, and flow automation, while mentoring junior engineers on STA fundamentals.
Matching Summary
Match Score: 85
NXP USA INC. is seeking an experienced Senior Static Timing Analysis (STA) Engineer to join their IC design team in Tianjin, China. This role involves leading timing signoff activities for complex SoC projects and requires strong collaboration with various design teams to ensure robust timing closure.
Skills & Requirements
Must-have
Static Timing Analysis (STA)
timing signoff
STA constraints (SDC)
timing methodologies
timing violations debug
timing optimization
timing models validation
MCMM timing closure
cross-functional collaboration
scripting skills (Tcl, Perl, Python, Shell)
Nice-to-have
technical leadership
methodology development
tool evaluation
flow automation
mentoring junior engineers
Key Requirements
Master’s degree in Electrical Engineering, Computer Engineering, or related field
5+ years of hands-on STA experience in SoC development
Strong English communication skills
Proficiency with Synopsys PrimeTime or Cadence Tempus
Solid understanding of OCV/AOCV/POCV, clock tree synthesis, crosstalk, IP timing integration, and MCMM flows
Familiarity with synthesis, place-and-route, and ECO flows
Expertise with SDC constraints and timing debugging