You will be crucial in translating RTL designs into optimized gate-level netlists, ensuring performance, power, and area targets are met for complex IP blocks
Job Summary
You will be crucial in translating RTL designs into optimized gate-level netlists, ensuring performance, power, and area targets are met for complex IP blocks.
The role involves collaborating closely with RTL designers, DFT engineers, and physical design engineers to ensure seamless integration and hand-off.
You will develop and maintain automation scripts and evaluate new CAD tools and methodologies to improve efficiency and design quality.
Matching Summary
You will be crucial in translating RTL designs into optimized gate-level netlists, ensuring performance, power, and area targets are met for complex IP blocks.
Skills & Requirements
Must-have
RTL synthesis and optimization
Static timing analysis (STA)
Formal verification (LEC)
Power and area optimization
Scripting for automation (Tcl, Python, Perl)
Industry-standard synthesis tools
Nice-to-have
Knowledge of DFT principles
Collaborative team environment
Integration with physical design teams
Key Requirements
Bachelor's or Master's degree in Electrical or Computer Engineering
2+ years experience in digital ASIC/SoC design
Proficiency with Synopsys Design Compiler or similar tools
Strong understanding of Synopsys PrimeTime or equivalent STA tools
Experience with Synopsys Formality or Cadence Conformal (LEC)