Senior Dft Timing Signoff Engineer (sta)

Intel Jobs

Folsom, California, US
Base: $164,470.00-$269,100.00 usd; bonus/equity: s...
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Primetime-based dft-mode timing signoff
Tessent dft architecture and implementation
Dft timing constraints (sdc) development
** Intel is seeking a Senior DFT Timing Signoff Engineer with extensive experience in DFT and STA for complex SoCs, focusing on PrimeTime-based signoff and DFT architecture. The role involves collaborating with various teams to ensure DFT-mode timing constraints and signoff readiness for next-generation AI processors. **

Job Summary

  • Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world.
  • The role involves owning DFT timing constraints and PrimeTime signoff for next-generation AI processors, collaborating closely with architecture, RTL, physical design, and test engineering teams.
  • Intel offers a total compensation package that ranks among the best in the industry, including competitive pay, stock bonuses, and benefit programs such as health, retirement, and vacation.

Matching Summary

Match Score: 75

** Intel is seeking a Senior DFT Timing Signoff Engineer with extensive experience in DFT and STA for complex SoCs, focusing on PrimeTime-based signoff and DFT architecture. The role involves collaborating with various teams to ensure DFT-mode timing constraints and signoff readiness for next-generation AI processors. **

Salary

Base: $164,470.00-$269,100.00 USD; Bonus/Equity: Stock bonuses; Benefits: Health, retirement, vacation

Skills & Requirements

Must-have

  • PrimeTime-based DFT-mode timing signoff
  • Tessent DFT architecture and implementation
  • DFT timing constraints (SDC) development
  • Streaming Scan Network (SSN) integration
  • IJTAG/test access integration
  • MBIST/BISR memory test and repair
  • Tcl scripting for automation

Nice-to-have

  • Python and shell scripting
  • Cross-team collaboration under aggressive schedules
  • Signoff guardrails and quality checks experience
  • Low-power intent checks
  • Debugging gate-level netlists
  • Regression and constraints hygiene strategies

Key Requirements

  • Bachelors & 8+ years or Masters & 6+ years in Electrical or Computer Engineering
  • 6+ years experience in DFT and/or STA for complex SoCs
  • Ownership of PrimeTime-only signoff environment
  • Experience with CDC/RDC fundamentals
  • Verilog/SystemVerilog proficiency
  • Tcl required; Python and/or shell preferred

Work Rights

Not specified

Tailored Resume

Cover Letter