Senior Asic Design Verification Engineer

Ethernovia

San Jose, CA, United States
Base: $200,000 - $300,000; bonus/equity: pre-ipo i...
On-site
Verilog/system verilog
Uvm
Python, tcl, c/c++
Responsible for all aspects of digital SoC verification, working with architects, designers, and SW engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems

Job Summary

  • Responsible for all aspects of digital SoC verification, working with architects, designers, and SW engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems.
  • The company is developing the future of Ethernet-based networks for software-defined and autonomous vehicles, robotics, and intelligent machines.
  • Ethernovia offers pre-IPO stock options, competitive compensation, and a full range of medical and other benefits.

Matching Summary

Responsible for all aspects of digital SoC verification, working with architects, designers, and SW engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems.

Salary

Base: $200,000 - $300,000; Bonus/Equity: Pre-IPO ISO options; Benefits: Medical, dental, and vision insurance

Skills & Requirements

Must-have

  • Verilog/System Verilog
  • UVM
  • Python, TCL, C/C++
  • Full verification flow
  • Debugging failures in simulation

Nice-to-have

  • Networking protocols
  • Third party IP integration
  • Modular and reusable testbench architecture
  • Design for re-use
  • Automation of testbench creation

Key Requirements

  • Minimum 10+ years of ASIC verification experience
  • BS and/or MS in Electrical Engineering, Computer Science, or related field

Work Rights

Not specified

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