Principal Physical Design Engineer

NXP USA INC.

Multiple Locations
On-site
Floor planning, power grid design, place and route
Low power implementation, clock tree synthesis
Timing closure, power/signal integrity analysis
NXP USA Inc. is seeking a Principal Physical Design Engineer with extensive experience in semiconductor integrated circuits to lead physical design projects. The role involves mentoring junior engineers and driving technical solutions to ensure timely delivery of high-performance products

Job Summary

  • Lead and contribute to the physical design and implementation of complex, high-performance semiconductor integrated circuits.
  • Drive the definition and implementation of physical design methodologies, flows, and best practices to optimize performance, power, and area.
  • Mentor and provide technical guidance to junior and senior physical design engineers, fostering a culture of continuous learning and excellence.

Matching Summary

Match Score: 85

NXP USA Inc. is seeking a Principal Physical Design Engineer with extensive experience in semiconductor integrated circuits to lead physical design projects. The role involves mentoring junior engineers and driving technical solutions to ensure timely delivery of high-performance products.

Skills & Requirements

Must-have

  • Floor planning, power grid design, place and route
  • Low power implementation, clock tree synthesis
  • Timing closure, power/signal integrity analysis
  • Physical verification (DRC/LVS/Antenna)
  • Static Timing Analysis (STA)
  • Power integrity (IR drop) and signal integrity (Crosstalk) analysis
  • Expert-level proficiency with EDA tools (Cadence Innovus, Synopsys Fusion Compiler/ICC2, Ansys RedHawk/PowerSI)
  • Proficiency in scripting languages (Tcl, Python, Perl)

Nice-to-have

  • Experience at top-level
  • Fostering a culture of continuous learning and excellence
  • Evaluate and adopt new EDA tools and technologies

Key Requirements

  • Bachelor's degree with 12+ years of experience or Master's degree with 10+ years of experience
  • Working knowledge on advance tech nodes 16ff and below
  • Extensive knowledge and experience in back-end implementation tasks
  • Deep understanding of Static Timing Analysis (STA) concepts
  • Strong knowledge of power analysis and optimization techniques (UPF/CPF)
  • Proven experience with physical verification tools (Synopsys IC Validator, Cadence Pegasus/PVS, Mentor Calibre)
  • Solid understanding of semiconductor device physics, process technology effects, and DFM/DFY considerations

Work Rights

Not specified

Tailored Resume

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