Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, from requirements decomposition to signoff
Job Summary
Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, from requirements decomposition to signoff.
Architect and implement UVM environments with scalable, reusable components, and develop test content including constrained-random sequences and assertions.
Collaborate cross-functionally with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule.
Matching Summary
Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, from requirements decomposition to signoff.
Skills & Requirements
Must-have
UVM/SystemVerilog testbench development
constrained-random test content
coverage closure
debug across levels
cross-functional collaboration
scripting proficiency
Nice-to-have
leading small teams
mentoring
driving signoff for tapeout
power-aware verification
emulation/FPGA prototyping
Key Requirements
5+ years SoC/IP design verification experience
BS/MS in Electrical/Computer Engineering or related field