High Level Synthesis Compiler Engineer

Altera

Toronto, Ontario, Canada
$139,000 – $201,250 cad py
Mlir and clang/llvm internals
Hls compiler infrastructure development
C++/sycl to hdl compilation flow
Lead the design, development, and optimization of HLS compiler infrastructure, focusing on MLIR and Clang

Job Summary

  • Lead the design, development, and optimization of HLS compiler infrastructure, focusing on MLIR and Clang.
  • Architect and implement new compiler passes, analyses, and code transformations to improve synthesis quality and performance.
  • Analyze and optimize the compilation flow from C++/SYCL to hardware description languages.

Matching Summary

Lead the design, development, and optimization of HLS compiler infrastructure, focusing on MLIR and Clang.

Salary

$139,000 – $201,250 CAD

Skills & Requirements

Must-have

  • MLIR and Clang/LLVM internals
  • HLS compiler infrastructure development
  • C++/SYCL to HDL compilation flow
  • Parallelism and pipelining optimization

Nice-to-have

  • Open-source contributions
  • FPGA or ASIC design flows
  • High-level hardware programming models

Key Requirements

  • 5+ years of compiler development experience
  • Strong background in HLS flows
  • Proficiency in C++ (modern standards)
  • Bachelor’s, Master’s, or Ph.D. in CS/EE or related field

Work Rights

Not specified

Tailored Resume

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